The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a bi-layer embedded stressor element for n-channel field effect transistors (nFETs) which greatly minimizes defect density and is implant damage free as well as a method of fabricating the bi-layer nFET embedded stressor element.
Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance such as, for example drive current. For example, in common silicon technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel region of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded SiGe or Si:C stressors (i.e., stress wells) within the source and drain regions of a complementary metal oxide semiconductor (CMOS) device to induce compressive or tensile strain in the channel region located between the source region and the drain region. For example, it has been demonstrated that hole mobility can be enhanced significantly in p-channel silicon transistors by using an embedded SiGe stressor in the source and drain regions. For re-channel silicon transistors, it has also been demonstrated that the electron mobility can be enhanced by using selective Si:C in which C is substitutional.
When the Si:C stressor includes a high content of C in substitutional sites of Si, a higher tensile strain can be applied to the Si channel. However, it is extremely difficult to obtain selectivity to oxide and nitride with a high content of C in the substitutional sites of Si due to extremely low carbon solubility (on the order of less than 10−6) in Si and the incompatibility of the Si:C precursor reactant gas to obtain selectivity.
Moreover, the integration of embedded Si:C into a typical complementary metal oxide semiconductor (CMOS) process is difficult because either the implantation process or the anneal process can completely relax the embedded Si:C. In prior art processes including an embedded Si:C stressor, high defect density is generated and dopant diffusion is uncontrollable in the embedded Si:C stressor.